1. Field of the Invention
The present invention relates to a signal processing circuit, a solid-state imaging device represented by a CMOS image sensor, and a camera system.
2. Description of the Related Art
A CMOS image sensor can be manufactured using the same manufacturing processes as a typical CMOS integrated circuit and can be driven with a single power source. In addition, analog circuits or logic circuits can be manufactured to coexist in a single chip using the CMOS processes.
Accordingly, that the CMOS image sensor has many advantages such as that the number of peripheral ICs can be reduced.
The mainstream of the output circuit of a CCD is a one-channel (ch) output type employing an FD amplifier having a floating diffusion (FD) layer.
In contrast, the CMOS image sensor includes an FD amplifier for each pixel and the mainstream of the output thereof is a parallel-column output type in which a row is selected out of a pixel array and pixels of the selected row are simultaneously read in the column direction.
This is because it is difficult to obtain the sufficient driving capability by the use of the FD amplifiers disposed in the pixels, it is thus necessary to lower the data rate, and the parallel process is advantageous.
Various circuits have been suggested as a pixel signal reading (output) circuit of the parallel-column output type CMOS image sensor.
In a most advanced type thereof, an analog-digital converter (hereinafter, abbreviated as “ADC”) is provided for each column and a pixel signal is extracted as a digital signal.
Such a CMOS image sensor mounted with a parallel-column ADC is disclosed, for example, in W. Yang et al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February, 1999 (non-patent document 1), or JP-A-2005-278135 (patent document 1).
FIG. 1 is a block diagram illustrating the configuration of a solid-state imaging device (CMOS image sensor) mounted with a parallel-column ADC.
As shown in FIG. 1, the solid-state imaging device 1 includes a pixel unit 2, a vertical scanning circuit 3, a horizontal transfer scanning circuit 4, and a column processing circuit group 5 including an ADC group.
The solid-state imaging device 1 further includes a digital-analog converter (hereinafter, abbreviated as “DAC”) 6 as a reference signal generating circuit and a sense amplifier (S/A) 7.
The pixel unit 2 has a configuration in which unit pixels 21 each including a photodiode (photoelectric conversion element) and an intra-pixel amplifier are arranged in a matrix shape.
In the column processing circuit group 5, plural column processing circuits 51 constituting an ADC for each column are arranged.
Each column processing circuit (ADC) 51 includes a comparator 51-1 that compares an analog signal acquired from the pixels of each row via a vertical signal line with a reference signal RAMP (Vslop) of a ramp waveform (RAMP) which is obtained by changing a reference, signal generated from the DAC 6 in a step shape.
Each column processing circuit 51 further includes a counter latch (memory) 51-2 that counts a comparison time of the comparator 51-1 and latches the counted result.
The column processing circuit 51 has an n-bit digital signal converting function and is disposed for each of the vertical signal lines (column lines) 8-1 to 8-n, whereby a parallel-column ADC block is constructed.
The output of each memory 51-2 is connected to, for example, a horizontal transfer line 9 with a k-bit width.
Here, k sense amplifiers 7 corresponding to the horizontal transfer line 9 are arranged.
FIG. 2 is a timing diagram of the circuit shown in FIG. 1.
In each column processing circuit (ADC) 51, an analog signal (with a potential of Vs1) read to the vertical signal line 8 is compared with the reference signal RAMP (Vslop) varying step-like by the comparator 51-1 disposed for each column.
At this time, the counter latch 51-2 counts until the analog potential Vs1 and the level of the reference signal RAMP (Vslop) intersect each other and the output of the comparator 51-1 is inverted, and the potential (analog signal) Vs1 of the vertical signal line 8 is converted into a digital signal (that is, converted in an AD conversion manner).
The AD conversion is performed two times for one reading operation.
In the first AD conversion, reset levels (P phase) of the unit pixels 21 are read to the vertical signal line 8 (8-1 to 8-n) and the AD conversion is performed thereon.
The P phase of the reset levels includes individual differences of the pixels.
In the second AD conversion, signals (D phase) photoelectrically converted by the unit pixels 21 are read to the vertical signal line 8 (8-1 to 8-n) and the AD conversion is performed thereon.
Since the D phase also includes the individual differences of the pixels, the correlated double sampling (CDS) can be embodied by performing a subtraction of (D-phase level-P-phase level).
The signals converted into the digital signals are recorded in the counter latch 51-2, are sequentially read to the sense amplifier 7 via the horizontal transfer line 9 by the horizontal (column) transfer scanning circuit 4, and are finally output.
In this way, the parallel-column output process is performed.
The counting process in the counter latch 51-2 for the P phase is referred to as a first sampling and the counting process in the counter latch 51-2 for the D phase is referred to as a second sampling.